- Small-footprint (small as 2KB, automatic scaling)
- Fast execution (sub microsecond context switch)
- Supports all popular processors and tools (see below)
- TraceX system analysis support
- Advanced Technology:
- Event Chaining™
- Performance Metrics
- Execution Profiling
- Run-time and Static Stack Analysis
- Multicore Support (SMP and AMP)
- Downloadable Application Modules
- Memory Protection for Downloadable Application Modules
- Extensive ThreadX ecosystem
- Safety Certifications (DO-178B, FDA510(k), IEC61508, etc)
- Deployed in over 1,000,000,000 devices
- Full Source Code
- Critical Link MityDSP/MityARM
- Energy Micro EFM32
- Fujitsu FM3
- Hitachi H8/300H
- Infineon XMC
- Microchip PIC24/dsPIC
- Microchip PIC32
- Nios II
- Power Architecture
- Renesas RX
- Renesas SH
- Renesas V8xx
- ST Microelectronics STM32
- Synopsys ARC
- TI ARM
- TI MSP430
- Univers A2P
- Xilinx ARM
ThreadX for ARC Microprocessors
Complete ARC support Reasonable pricing No Royalties Complete ANSI C source code Easy to use and powerful services Responsive Technical Support Unlimited Threads, Queues, Event Flags, Timers, Semaphores, Mutexes, Block Pools, and Byte Pools Flexible memory usage Timeout available on all thread suspension Advanced preemption-threshold technique Low-overhead Application Timers Size scales automatically picokernel architecture for size and speed Small footprint (Instruction area size: 4-25K) Fast Execution (100MHz, 0 wait-states, ARC)
Improve Your ARC Development
Let our extensive experience with the ARC family of microprocessors help your product development. ThreadX, our high-performance real-time kernel, helps improve your product's quality and its time-to-market. In addition, using ThreadX makes it easier to enhance your product in the future.
ThreadX optimizes context switching on the ARC processor. When context switching occurs inside of a ThreadX service call, only the registers preserved across function calls are saved as part of the thread's context, i.e. registers r13-r26, fp, and blink.
A similar technique is used in interrupt handling. On the front end of interrupt service routines, only the compiler's scratch registers are saved initially (registers r0-r12). The full register set is saved only if thread preemption is required.
Fast Level2 Interrupt Response
ARC Level2 interrupts are left completely enabled throughout ThreadX processing, resulting in the fastest possible response.
MetaWare Development Toolkit Support
ThreadX is completely compatible with the advanced DesignWare® ARC™ MetaWare Development Toolkit from Synopsys, Inc. You are up and running right out of the box!
The DesignWare® ARC™ MetaWare Development Toolkit builds upon a 25-year legacy of industry-leading compiler and debugger products. It is a complete solution that contains all the components needed to support the development, debugging and tuning of embedded applications for the DesignWare ARC processors. The tool chain supports the complete family of ARC Processors, from the deeply embedded ARC EM Family to the general-purpose ARC 600 Family and the ARC 700 Family for high-performance applications.
The DesignWare ARC MetaWare C Compiler is ANSI-C compliant, and supports the relevant subset of the ISO extensions for embedded applications. The C++ compiler supports advanced language features like partial specialization of class templates, and comes with a Standard Template Library next to the standard C++ library. For embedded developers targeting their applications to the DesignWare ARC processor architecture, the compilers deliver industry-leading code density while maximizing performance. Synopsys maintains and runs an extensive suite of internal compiler verification and validation tests, and runs C and C++ validation suites from Plum Hall, Inc. and Perennial, Inc. prior to every product release.