- Small-footprint (small as 2KB, automatic scaling)
- Fast execution (sub microsecond context switch)
- Supports all popular processors and tools (see below)
- TraceX system analysis support
- Advanced Technology:
- Preemption-Threshold™
- Event Chaining™
- Performance Metrics
- Execution Profiling
- Run-time and Static Stack Analysis
- Multicore Support (SMP and AMP)
- Downloadable Application Modules
- Memory Protection for Downloadable Application Modules
- Extensive ThreadX ecosystem
- Safety Certifications (DO-178B, FDA510(k), IEC61508, etc)
- Deployed in over 1,000,000,000 devices
- Full Source Code
- Royalty-Free
- ARM
- Atmel
- BlackFin
- CEVA-TeakLite-III
- ColdFire/68K
- Critical Link MityDSP/MityARM
- Energy Micro EFM32
- Freescale
- Fujitsu FM3
- G-Series
- Hitachi H8/300H
- Infineon XMC
- Leon3
- M-CORE
- MicroBlaze
- Microchip PIC24/dsPIC
- Microchip PIC32
- MIPS
- Nios II
- NXP
- Power Architecture
- Renesas RX
- Renesas SH
- Renesas V8xx
- SHARC
- ST Microelectronics STM32
- StarCore
- StrongARM
- Synopsys ARC
- TI ARM
- TI MSP430
- TMS320C54x
- TMS320C6x
- Univers A2P
- Win32
- x86/x386
- Xilinx ARM
- XScale
- Xtensa/Diamond
SHARC
ThreadX for Analog Devices SHARC Microprocessors
Highlights
Complete ADSP-2106x family support Reasonable pricing No Royalties Complete ANSI C source code Easy to use and powerful services Responsive Technical Support Unlimited Threads, Queues, Event Flags, Timers, Semaphores, Mutexes, Block Pools, and Byte Pools Flexible memory usage Timeout available on all thread suspension Advanced preemption-threshold technique Low-overhead Application Timers Size scales automatically picokernel architecture for size and speed Small footprint (Instruction area size: 6.5-30K) Fast Execution (ADSP-21060@40MIPS)
Improve Your SHARC Development
Let our extensive experience with the ADSP-2106x family of microprocessors help your product development. ThreadX, our high-performance real-time kernel, helps improve your product's quality and its time-to-market. In addition, using ThreadX makes it easier to enhance your product in the future.
SHARC Optimizations
ThreadX optimizes context switching on the SHARC. When context switching occurs inside of a ThreadX service call, only the registers preserved across function calls are saved as part of the thread's context-registers.
A similar technique is used in interrupt handling. On the front end of interrupt service routines, only the compiler's scratch registers are saved initially. The full register set is saved only if thread preemption is required.
Delay Slot Usage
ThreadX takes full advantage of SHARC branch delay slots for enhanced performance.
Easy to Use
ThreadX is designed for ease of use. Our API is designed to be easy to understand, powerful and consistent. The same is true with our reference manual and other supporting documentaion.
