threadx Snapshot
  • Small-footprint (small as 2KB, automatic scaling)
  • Fast execution (sub microsecond context switch)
  • Supports all popular processors and tools (see below)
  • TraceX system analysis support
  • Advanced Technology:
    • Preemption-Threshold™
    • Event Chaining™
    • Performance Metrics
    • Execution Profiling
    • Run-time and Static Stack Analysis
    • Multicore Support (SMP and AMP)
    • Downloadable Application Modules
    • Memory Protection for Downloadable Application Modules
  • Extensive ThreadX ecosystem
  • Safety Certifications (DO-178B, FDA510(k), IEC61508, etc)
  • Deployed in over 1,000,000,000 devices
  • Full Source Code
  • Royalty-Free
threadx Processor Support

Xtensa/Diamond

ThreadX for Xtensa/Diamond

Highlights

  • Complete support for Tensilica's Configurable Xtensa and Diamond Cores
  • Reasonable pricing
  • No Royalties
  • Complete ANSI C source code
  • Easy to use and powerful services
  • Responsive Technical Support
  • Unlimited Threads, Queues, Event Flags, Timers, Semaphores, Mutexes, Block Pools, and Byte Pools
  • Flexible memory usage
  • Timeout available on all thread suspension
  • Advanced preemption-threshold technique
  • Low-overhead Application Timers · Size scales automatically
  • Picokernel architecture for size and speed
  • Small footprint (as low as 7.5 Kbytes)
  • Fast Execution (1.3us context switch@200MHz)
  • Improve Your Xtensa/Diamond Development

    Let our extensive experience with the Xtensa/Diamond family of microprocessors help your product development. ThreadX, our high-performance real-time kernel, helps improve your product's quality and its time-to-market. In addition, using ThreadX makes it easier to enhance your product in the future.

    Xtensa/Diamond Optimizations

    ThreadX optimizes context switching on the Xtensa/Diamond processors. When context switching occurs inside of a ThreadX service call, only the registers preserved across function calls are saved as part of the thread's context. The full register set is saved only if thread preemption is required as a result of an interrupt.