threadx Snapshot
  • Small-footprint (small as 2KB, automatic scaling)
  • Fast execution (sub microsecond context switch)
  • Supports all popular processors and tools (see below)
  • TraceX system analysis support
  • Advanced Technology:
    • Preemption-Threshold™
    • Event Chaining™
    • Performance Metrics
    • Execution Profiling
    • Run-time and Static Stack Analysis
    • Multicore Support (SMP and AMP)
    • Downloadable Application Modules
    • Memory Protection for Downloadable Application Modules
  • Extensive ThreadX ecosystem
  • Safety Certifications (DO-178B, FDA510(k), IEC61508, etc)
  • Deployed in over 1,000,000,000 devices
  • Full Source Code
  • Royalty-Free
threadx Processor Support

CEVA-TeakLite-III

ThreadX for CEVA-TeakLite-III

Highlights

  • Complete CEVA-TeakLite-III support
  • Fully Integrated with the CEVA Tools
  • Reasonable pricing
  • No Royalties
  • Complete ANSI C source code
  • Easy to use and powerful services
  • Responsive Technical Support
  • Unlimited Threads, Queues, Event Flags, Timers, Semaphores, Mutexes, Block Pools, and Byte Pools
  • Flexible memory usage
  • Timeout available on all thread suspension
  • Advanced preemption-threshold technique
  • Low-overhead Application Timers
  • Size scales automatically
  • Picokernel architecture for size and speed
  • Small footprint (as low as 1.2 Kwords)
  • Fast Execution (0.14us context switch@700MHz)
  • Improve Your CEVA-TeakLite-III Development

    Let our extensive experience with the CEVA-TeakLite-III family of microprocessors help your product development. ThreadX, our high-performance real-time kernel, helps improve your product's quality and its time-to-market. In addition, using ThreadX makes it easier to enhance your product in the future.

    CEVA-TeakLite-III Optimizations

    ThreadX optimizes context switching on the CEVA-TeakLite-III. When context switching occurs inside of a ThreadX service call, only the registers preserved across function calls are saved as part of the thread's context. A similar technique is used in interrupt handling. On the front end of interrupt service routines, only the compiler's scratch registers are saved initially. The full register set is saved only if thread preemption is required.

    Flexible Interrupt Model

    ThreadX supports the variety of shadow register options on the CEVA-TeakLite-III as well as the stack-based register architecture of the CEVA-TeakLite-III. All interrupt processing uses a separate system stack and as mentioned previously, full context saving/restoring is performed only when thread preemption is necessary.

    Nested Interrupt Handling

    ThreadX also fully supports nested interrupts.

    Evaluation Board Support

    ThreadX demonstrations are available for the CEVA-TeakLite-III evaluation platform.

    Development Tools

    ThreadX is fully integrated with the CEVA-TeakLite-III development suite.